forked from Mirrors/tinycc
arm64-gen.c: Avoid some cases of undefined behaviour.
Also make some functions more portable.master
Edmund Grimley Evans
parent
c52128c581
commit
a7334f791d
99
arm64-gen.c
99
arm64-gen.c
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@ -286,26 +286,28 @@ static void arm64_spoff(int reg, uint64_t off)
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}
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}
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static void arm64_ldrx(int sg, int sz, int dst, int bas, uint64_t off)
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static void arm64_ldrx(int sg, int sz_, int dst, int bas, uint64_t off)
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{
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uint32_t sz = sz_;
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if (sz >= 2)
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sg = 0;
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if (!(off & ~(0xfff << sz)))
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if (!(off & ~((uint32_t)0xfff << sz)))
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o(0x39400000 | dst | bas << 5 | off << (10 - sz) |
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!!sg << 23 | sz << 30); // ldr(*) x(dst),[x(bas),#(off)]
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(uint32_t)!!sg << 23 | sz << 30); // ldr(*) x(dst),[x(bas),#(off)]
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else if (off < 256 || -off <= 256)
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o(0x38400000 | dst | bas << 5 | (off & 511) << 12 |
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!!sg << 23 | sz << 30); // ldur(*) x(dst),[x(bas),#(off)]
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(uint32_t)!!sg << 23 | sz << 30); // ldur(*) x(dst),[x(bas),#(off)]
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else {
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arm64_movimm(30, off); // use x30 for offset
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o(0x38206800 | dst | bas << 5 | 30 << 16 |
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(!!sg + 1) << 22 | sz << 30); // ldr(*) x(dst),[x(bas),x30]
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o(0x38206800 | dst | bas << 5 | (uint32_t)30 << 16 |
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(uint32_t)(!!sg + 1) << 22 | sz << 30); // ldr(*) x(dst),[x(bas),x30]
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}
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}
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static void arm64_ldrv(int sz, int dst, int bas, uint64_t off)
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static void arm64_ldrv(int sz_, int dst, int bas, uint64_t off)
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{
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if (!(off & ~(0xfff << sz)))
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uint32_t sz = sz_;
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if (!(off & ~((uint32_t)0xfff << sz)))
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o(0x3d400000 | dst | bas << 5 | off << (10 - sz) |
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(sz & 4) << 21 | (sz & 3) << 30); // ldr (s|d|q)(dst),[x(bas),#(off)]
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else if (off < 256 || -off <= 256)
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@ -313,13 +315,14 @@ static void arm64_ldrv(int sz, int dst, int bas, uint64_t off)
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(sz & 4) << 21 | (sz & 3) << 30); // ldur (s|d|q)(dst),[x(bas),#(off)]
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else {
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arm64_movimm(30, off); // use x30 for offset
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o(0x3c606800 | dst | bas << 5 | 30 << 16 | sz << 30 | (sz & 4) << 21);
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// ldr (s|d|q)(dst),[x(bas),x30]
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o(0x3c606800 | dst | bas << 5 | (uint32_t)30 << 16 |
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sz << 30 | (sz & 4) << 21); // ldr (s|d|q)(dst),[x(bas),x30]
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}
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}
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static void arm64_ldrs(int reg, int size)
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static void arm64_ldrs(int reg_, int size)
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{
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uint32_t reg = reg_;
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// Use x30 for intermediate value in some cases.
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switch (size) {
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default: assert(0); break;
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@ -395,9 +398,10 @@ static void arm64_ldrs(int reg, int size)
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}
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}
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static void arm64_strx(int sz, int dst, int bas, uint64_t off)
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static void arm64_strx(int sz_, int dst, int bas, uint64_t off)
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{
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if (!(off & ~(0xfff << sz)))
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uint32_t sz = sz_;
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if (!(off & ~((uint32_t)0xfff << sz)))
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o(0x39000000 | dst | bas << 5 | off << (10 - sz) | sz << 30);
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// str(*) x(dst),[x(bas],#(off)]
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else if (off < 256 || -off <= 256)
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@ -405,14 +409,15 @@ static void arm64_strx(int sz, int dst, int bas, uint64_t off)
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// stur(*) x(dst),[x(bas],#(off)]
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else {
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arm64_movimm(30, off); // use x30 for offset
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o(0x38206800 | dst | bas << 5 | 30 << 16 | sz << 30);
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o(0x38206800 | dst | bas << 5 | (uint32_t)30 << 16 | sz << 30);
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// str(*) x(dst),[x(bas),x30]
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}
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}
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static void arm64_strv(int sz, int dst, int bas, uint64_t off)
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static void arm64_strv(int sz_, int dst, int bas, uint64_t off)
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{
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if (!(off & ~(0xfff << sz)))
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uint32_t sz = sz_;
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if (!(off & ~((uint32_t)0xfff << sz)))
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o(0x3d000000 | dst | bas << 5 | off << (10 - sz) |
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(sz & 4) << 21 | (sz & 3) << 30); // str (s|d|q)(dst),[x(bas),#(off)]
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else if (off < 256 || -off <= 256)
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@ -420,8 +425,8 @@ static void arm64_strv(int sz, int dst, int bas, uint64_t off)
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(sz & 4) << 21 | (sz & 3) << 30); // stur (s|d|q)(dst),[x(bas),#(off)]
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else {
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arm64_movimm(30, off); // use x30 for offset
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o(0x3c206800 | dst | bas << 5 | 30 << 16 | sz << 30 | (sz & 4) << 21);
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// str (s|d|q)(dst),[x(bas),x30]
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o(0x3c206800 | dst | bas << 5 | (uint32_t)30 << 16 |
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sz << 30 | (sz & 4) << 21); // str (s|d|q)(dst),[x(bas),x30]
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}
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}
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@ -458,7 +463,8 @@ ST_FUNC void load(int r, SValue *sv)
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int svtt = sv->type.t;
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int svr = sv->r & ~VT_LVAL_TYPE;
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int svrv = svr & VT_VALMASK;
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uint64_t svcul = (int32_t)sv->c.ul;
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uint64_t svcul = (uint32_t)sv->c.ul;
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svcul = svcul >> 31 & 1 ? svcul - ((uint64_t)1 << 32) : svcul;
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if (svr == (VT_LOCAL | VT_LVAL)) {
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if (IS_FREG(r))
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@ -519,7 +525,7 @@ ST_FUNC void load(int r, SValue *sv)
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o(0xd10003a0 | intr(r) | -svcul << 10); // sub x(r),x29,#...
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else {
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arm64_movimm(30, -svcul); // use x30 for offset
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o(0xcb0003a0 | intr(r) | 30 << 16); // sub x(r),x29,x30
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o(0xcb0003a0 | intr(r) | (uint32_t)30 << 16); // sub x(r),x29,x30
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}
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return;
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}
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@ -552,7 +558,8 @@ ST_FUNC void store(int r, SValue *sv)
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int svtt = sv->type.t;
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int svr = sv->r & ~VT_LVAL_TYPE;
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int svrv = svr & VT_VALMASK;
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uint64_t svcul = (int32_t)sv->c.ul;
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uint64_t svcul = (uint32_t)sv->c.ul;
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svcul = svcul >> 31 & 1 ? svcul - ((uint64_t)1 << 32) : svcul;
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if (svr == (VT_LOCAL | VT_LVAL)) {
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if (IS_FREG(r))
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@ -594,7 +601,7 @@ static void arm64_gen_bl_or_b(int b)
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o(0x94000000); // bl .
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}
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else
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o(0xd61f0000 | !b << 21 | intr(gv(RC_R30)) << 5); // br/blr
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o(0xd61f0000 | (uint32_t)!b << 21 | intr(gv(RC_R30)) << 5); // br/blr
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}
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static int arm64_hfa_aux(CType *type, int *fsize, int num)
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@ -930,7 +937,7 @@ ST_FUNC void gfunc_call(int nb_args)
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else if (a[i] < 32) {
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// value in floating-point registers
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if ((vtop->type.t & VT_BTYPE) == VT_STRUCT) {
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int j, sz, n = arm64_hfa(&vtop->type, &sz);
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uint32_t j, sz, n = arm64_hfa(&vtop->type, &sz);
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vtop->type.t = VT_PTR;
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gaddrof();
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gv(RC_R30);
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@ -968,7 +975,7 @@ ST_FUNC void gfunc_call(int nb_args)
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if (bt == VT_BYTE || bt == VT_SHORT)
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// Promote small integers:
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o(0x13001c00 | (bt == VT_SHORT) << 13 |
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!!(rt & VT_UNSIGNED) << 30); // [su]xt[bh] w0,w0
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(uint32_t)!!(rt & VT_UNSIGNED) << 30); // [su]xt[bh] w0,w0
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else if (bt == VT_STRUCT && !(a[0] & 1)) {
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// A struct was returned in registers, so write it out:
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gv(RC_R(8));
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@ -983,7 +990,7 @@ ST_FUNC void gfunc_call(int nb_args)
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}
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else if (a[0] == 16) {
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int j, sz, n = arm64_hfa(return_type, &sz);
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uint32_t j, sz, n = arm64_hfa(return_type, &sz);
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for (j = 0; j < n; j++)
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o(0x3d000100 |
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(sz & 16) << 19 | -(sz & 8) << 27 | (sz & 4) << 29 |
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@ -1053,14 +1060,14 @@ ST_FUNC void gfunc_prolog(CType *func_type)
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(!(a[i] & 1) && size > 8)) * 8;
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}
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else if (a[i] < 32) {
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int hfa = arm64_hfa(&sym->type, 0);
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uint32_t hfa = arm64_hfa(&sym->type, 0);
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arm64_func_va_list_vr_offs = (a[i] / 2 - 16 +
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(hfa ? hfa : 1)) * 16;
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}
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// HFAs of float and double need to be written differently:
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if (16 <= a[i] && a[i] < 32 && (sym->type.t & VT_BTYPE) == VT_STRUCT) {
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int j, sz, k = arm64_hfa(&sym->type, &sz);
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uint32_t j, sz, k = arm64_hfa(&sym->type, &sz);
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if (sz < 16)
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for (j = 0; j < k; j++) {
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o(0x3d0003e0 | -(sz & 8) << 27 | (sz & 4) << 29 |
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@ -1196,7 +1203,8 @@ ST_FUNC void gen_va_arg(CType *t)
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}
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}
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ST_FUNC int gfunc_sret(CType *vt, int variadic, CType *ret, int *align, int *regsize)
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ST_FUNC int gfunc_sret(CType *vt, int variadic, CType *ret,
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int *align, int *regsize)
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{
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return 0;
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}
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@ -1231,7 +1239,7 @@ ST_FUNC void greturn(void)
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}
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case 16:
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if ((func_vt.t & VT_BTYPE) == VT_STRUCT) {
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int j, sz, n = arm64_hfa(&vtop->type, &sz);
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uint32_t j, sz, n = arm64_hfa(&vtop->type, &sz);
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gaddrof();
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gv(RC_R(0));
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for (j = 0; j < n; j++)
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@ -1304,7 +1312,7 @@ ST_FUNC int gtst(int inv, int t)
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{
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int bt = vtop->type.t & VT_BTYPE;
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if (bt == VT_LDOUBLE) {
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int a, b, f = fltr(gv(RC_FLOAT));
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uint32_t a, b, f = fltr(gv(RC_FLOAT));
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a = get_reg(RC_INT);
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vpushi(0);
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vtop[0].r = a;
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@ -1318,13 +1326,13 @@ ST_FUNC int gtst(int inv, int t)
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--vtop;
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}
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else if (bt == VT_FLOAT || bt == VT_DOUBLE) {
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int a = fltr(gv(RC_FLOAT));
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uint32_t a = fltr(gv(RC_FLOAT));
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o(0x1e202008 | a << 5 | (bt != VT_FLOAT) << 22); // fcmp
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o(0x54000040 | !!inv); // b.eq/b.ne .+8
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}
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else {
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int ll = (bt == VT_PTR || bt == VT_LLONG);
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int a = intr(gv(RC_INT));
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uint32_t ll = (bt == VT_PTR || bt == VT_LLONG);
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uint32_t a = intr(gv(RC_INT));
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o(0x34000040 | a | !!inv << 24 | ll << 31); // cbz/cbnz wA,.+8
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}
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--vtop;
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@ -1362,7 +1370,7 @@ static int arm64_gen_opic(int op, uint32_t l, int rev, uint64_t val,
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switch (op) {
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case '+': {
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int s = l ? val >> 63 : val >> 31;
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uint32_t s = l ? val >> 63 : val >> 31;
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val = s ? -val : val;
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val = l ? val : (uint32_t)val;
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if (!(val & ~(uint64_t)0xfff))
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@ -1470,7 +1478,8 @@ static void arm64_gen_opil(int op, uint32_t l)
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case '%':
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// Use x30 for quotient:
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o(0x1ac00c00 | l << 31 | 30 | a << 5 | b << 16); // sdiv
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o(0x1b008000 | l << 31 | x | 30 << 5 | b << 16 | a << 10); // msub
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o(0x1b008000 | l << 31 | x | (uint32_t)30 << 5 |
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b << 16 | a << 10); // msub
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break;
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case '&':
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o(0x0a000000 | l << 31 | x | a << 5 | b << 16); // and
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@ -1549,7 +1558,8 @@ static void arm64_gen_opil(int op, uint32_t l)
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case TOK_UMOD:
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// Use x30 for quotient:
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o(0x1ac00800 | l << 31 | 30 | a << 5 | b << 16); // udiv
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o(0x1b008000 | l << 31 | x | 30 << 5 | b << 16 | a << 10); // msub
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o(0x1b008000 | l << 31 | x | (uint32_t)30 << 5 |
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b << 16 | a << 10); // msub
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break;
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default:
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assert(0);
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@ -1568,7 +1578,7 @@ ST_FUNC void gen_opl(int op)
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ST_FUNC void gen_opf(int op)
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{
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int x, a, b, dbl;
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uint32_t x, a, b, dbl;
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if (vtop[0].type.t == VT_LDOUBLE) {
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CType type = vtop[0].type;
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@ -1596,7 +1606,7 @@ ST_FUNC void gen_opf(int op)
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vtop->type = type;
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else {
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o(0x7100001f); // cmp w0,#0
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o(0x1a9f07e0 | cond << 12); // cset w0,(cond)
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o(0x1a9f07e0 | (uint32_t)cond << 12); // cset w0,(cond)
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}
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return;
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}
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@ -1668,7 +1678,7 @@ ST_FUNC void gen_opf(int op)
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// Generate sign extension from 32 to 64 bits:
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ST_FUNC void gen_cvt_sxtw(void)
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{
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int r = intr(gv(RC_INT));
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uint32_t r = intr(gv(RC_INT));
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o(0x93407c00 | r | r << 5); // sxtw x(r),w(r)
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}
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@ -1690,12 +1700,13 @@ ST_FUNC void gen_cvt_itof(int t)
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else {
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int d, n = intr(gv(RC_INT));
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int s = !(vtop->type.t & VT_UNSIGNED);
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int l = ((vtop->type.t & VT_BTYPE) == VT_LLONG);
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uint32_t l = ((vtop->type.t & VT_BTYPE) == VT_LLONG);
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--vtop;
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d = get_reg(RC_FLOAT);
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++vtop;
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vtop[0].r = d;
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o(0x1e220000 | !s << 16 | (t != VT_FLOAT) << 22 | fltr(d) |
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o(0x1e220000 | (uint32_t)!s << 16 |
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(uint32_t)(t != VT_FLOAT) << 22 | fltr(d) |
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l << 31 | n << 5); // [us]cvtf [sd](d),[wx](n)
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}
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}
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@ -1716,14 +1727,14 @@ ST_FUNC void gen_cvt_ftoi(int t)
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}
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else {
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int d, n = fltr(gv(RC_FLOAT));
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int l = ((vtop->type.t & VT_BTYPE) != VT_FLOAT);
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uint32_t l = ((vtop->type.t & VT_BTYPE) != VT_FLOAT);
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--vtop;
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d = get_reg(RC_INT);
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++vtop;
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vtop[0].r = d;
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o(0x1e380000 |
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!!(t & VT_UNSIGNED) << 16 |
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((t & VT_BTYPE) == VT_LLONG) << 31 | intr(d) |
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(uint32_t)!!(t & VT_UNSIGNED) << 16 |
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(uint32_t)((t & VT_BTYPE) == VT_LLONG) << 31 | intr(d) |
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l << 22 | n << 5); // fcvtz[su] [wx](d),[sd](n)
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}
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}
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