forked from Mirrors/tinycc
riscv: More insns, operands and arg slots
* load/store of FP ops * load/store from symbols, VT_LLOCAL, some with large addend * load of VT_JMP result * calls with many args (stack slots) * calls with FP args * more operations: and/or/xor/divmob
Michael Matz
parent
b1c7520886
commit
9214087259
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@ -360,7 +360,7 @@ if test -z "$cross_prefix" ; then
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fi
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if test -z "$triplet"; then
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if test $cpu = "x86_64" -o $cpu = "aarch64" ; then
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if test $cpu = "x86_64" -o $cpu = "aarch64" -o $cpu = "riscv64" ; then
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if test -f "/usr/lib64/crti.o" ; then
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tcc_lddir="lib64"
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fi
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240
riscv64-gen.c
240
riscv64-gen.c
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@ -34,6 +34,7 @@
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#define XLEN 8
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#define TREG_RA 17
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#define TREG_SP 18
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ST_DATA const int reg_classes[NB_REGS] = {
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RC_INT | RC_R(0),
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@ -58,13 +59,21 @@ static int ireg(int r)
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{
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if (r == TREG_RA)
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return 1; // ra
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if (r == TREG_SP)
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return 2; // sp
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assert(r >= 0 && r < 8);
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return r + 10; // tccrX --> aX == x(10+X)
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}
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static int is_ireg(int r)
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{
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return r < 8 || r == TREG_RA;
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return r < 8 || r == TREG_RA || r == TREG_SP;
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}
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static int freg(int r)
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{
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assert(r >= 8 && r < 16);
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return r - 8 + 10; // tccfX --> faX == f(10+X)
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}
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static int is_freg(int r)
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@ -122,37 +131,71 @@ ST_FUNC void load(int r, SValue *sv)
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{
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int fr = sv->r;
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int v = fr & VT_VALMASK;
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int rr = ireg(r);
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int rr = is_ireg(r) ? ireg(r) : freg(r);
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int fc = sv->c.i;
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int bt = sv->type.t & VT_BTYPE;
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int align, size = type_size(&sv->type, &align);
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if (fr & VT_LVAL) {
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int bt = sv->type.t & VT_BTYPE;
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int align, size = type_size(&sv->type, &align);
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int func3;
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if (is_float(bt))
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tcc_error("unimp: load-local(float)");
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else if (bt == VT_FUNC)
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size = PTR_SIZE;
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func3 = size == 1 ? 0 : size == 2 ? 1 : size == 4 ? 2 : 3;
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if (size < 8 && (sv->type.t & VT_UNSIGNED))
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func3 |= 4;
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int func3, opcode = 0x03;
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if (is_freg(r)) {
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assert(bt == VT_DOUBLE || bt == VT_FLOAT);
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opcode = 0x07;
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func3 = bt == VT_DOUBLE ? 3 : 2;
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} else {
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assert(is_ireg(r));
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if (bt == VT_FUNC)
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size = PTR_SIZE;
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func3 = size == 1 ? 0 : size == 2 ? 1 : size == 4 ? 2 : 3;
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if (size < 8 && !is_float(sv->type.t) && (sv->type.t & VT_UNSIGNED))
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func3 |= 4;
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}
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if (v == VT_LOCAL) {
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if (((unsigned)fc + (1 << 11)) >> 12)
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tcc_error("unimp: load(large local ofs) (0x%x)", fc);
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EI(0x03, func3, rr, 8, fc); // l[bhwd][u] RR, fc(s0)
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EI(opcode, func3, rr, 8, fc); // l[bhwd][u]/fl[wd] RR, fc(s0)
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} else if (v < VT_CONST) {
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EI(0x03, func3, rr, ireg(v), 0); // l[bhwd][u] RR, 0(V)
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/*if (((unsigned)fc + (1 << 11)) >> 12)
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tcc_error("unimp: load(large addend) (0x%x)", fc);*/
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fc = 0; // XXX store ofs in LVAL(reg)
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EI(opcode, func3, rr, ireg(v), fc); // l[bhwd][u] RR, 0(V)
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} else if (v == VT_CONST && (fr & VT_SYM)) {
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static Sym label;
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int addend = 0, tempr;
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if (1 || ((unsigned)fc + (1 << 11)) >> 12)
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addend = fc, fc = 0;
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greloca(cur_text_section, sv->sym, ind,
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R_RISCV_PCREL_HI20, addend);
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if (!label.v) {
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label.v = tok_alloc(".L0 ", 4)->tok;
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label.type.t = VT_VOID | VT_STATIC;
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}
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label.c = 0; /* force new local ELF symbol */
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put_extern_sym(&label, cur_text_section, ind, 0);
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tempr = is_ireg(r) ? rr : ireg(get_reg(RC_INT));
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o(0x17 | (tempr << 7)); // auipc TR, 0 %pcrel_hi(sym)+addend
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greloca(cur_text_section, &label, ind,
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R_RISCV_PCREL_LO12_I, 0);
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EI(opcode, func3, rr, tempr, fc); // l[bhwd][u] RR, fc(TR)
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} else if (v == VT_LLOCAL) {
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int tempr = rr;
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if (((unsigned)fc + (1 << 11)) >> 12)
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tcc_error("unimp: load(large local ofs) (0x%x)", fc);
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if (!is_ireg(r))
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tempr = ireg(get_reg(RC_INT));
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EI(0x03, 3, tempr, 8, fc); // ld TEMPR, fc(s0)
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EI(opcode, func3, rr, tempr, 0); // l[bhwd][u] RR, 0(TEMPR)
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} else {
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tcc_error("unimp: load(non-local lval)");
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}
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} else if (v == VT_CONST) {
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int rb = 0;
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assert(!is_float(sv->type.t) && is_ireg(r));
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if (fc != sv->c.i)
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tcc_error("unimp: load(very large const)");
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if (((unsigned)fc + (1 << 11)) >> 12)
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tcc_error("unimp: load(large const) (0x%x)", fc);
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if (fr & VT_SYM) {
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static Sym label;
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greloca(cur_text_section, vtop->sym, ind,
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greloca(cur_text_section, sv->sym, ind,
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R_RISCV_PCREL_HI20, fc);
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if (!label.v) {
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label.v = tok_alloc(".L0 ", 4)->tok;
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@ -164,24 +207,42 @@ ST_FUNC void load(int r, SValue *sv)
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greloca(cur_text_section, &label, ind,
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R_RISCV_PCREL_LO12_I, 0);
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rb = rr;
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fc = 0;
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}
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if (is_float(sv->type.t))
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tcc_error("unimp: load(float)");
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EI(0x13, 0, rr, rb, fc); // addi R, x0|R, FC
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if (((unsigned)fc + (1 << 11)) >> 12)
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o(0x37 | (rr << 7) | ((0x800 + fc) & 0xfffff000)), rb = rr; //lui RR, upper(fc)
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EI(0x13, 0, rr, rb, fc << 20 >> 20); // addi R, x0|R, FC
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} else if (v == VT_LOCAL) {
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assert(is_ireg(r));
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if (((unsigned)fc + (1 << 11)) >> 12)
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tcc_error("unimp: load(addr large local ofs) (0x%x)", fc);
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EI(0x13, 0, rr, 8, fc); // addi R, s0, FC
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} else if (v < VT_CONST) {
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/* reg-reg */
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//assert(!fc); XXX support offseted regs
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if (is_freg(r) && is_freg(v))
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tcc_error("unimp load: float reg-reg move");
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o(0x53 | (rr << 7) | (freg(v) << 15) | (freg(v) << 20) | ((bt == VT_DOUBLE ? 0x11 : 0x10) << 25)); //fsgnj.[sd] RR, V, V == fmv.[sd] RR, V
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else if (is_ireg(r) && is_ireg(v))
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EI(0x13, 0, rr, ireg(v), 0); // addi RR, V, 0 == mv RR, V
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else
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tcc_error("ICE: inter-unit reg-reg move");
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else {
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int func7 = is_ireg(r) ? 0x70 : 0x78;
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if (size == 8)
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func7 |= 1;
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assert(size == 4 || size == 8);
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o(0x53 | (rr << 7) | ((is_freg(v) ? freg(v) : ireg(v)) << 15)
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| (func7 << 25)); // fmv.{w.x, x.w, d.x, x.d} RR, VR
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}
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} else if (v == VT_CMP) { // we rely on cmp_r to be the correct result
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EI(0x13, 0, rr, vtop->cmp_r, 0); // mv RR, CMP_R
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} else if ((v & ~1) == VT_JMP) {
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int t = v & 1;
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assert(is_ireg(r));
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EI(0x13, 0, rr, 0, t); // addi RR, x0, t
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gjmp_addr(ind + 8);
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gsym(fc);
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EI(0x13, 0, rr, 0, t ^ 1); // addi RR, x0, !t
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} else
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tcc_error("unimp: load(non-const)");
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}
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@ -189,26 +250,58 @@ ST_FUNC void load(int r, SValue *sv)
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ST_FUNC void store(int r, SValue *sv)
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{
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int fr = sv->r & VT_VALMASK;
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int rr = ireg(r);
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int rr = is_ireg(r) ? ireg(r) : freg(r);
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int fc = sv->c.i;
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int ft = sv->type.t;
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int bt = ft & VT_BTYPE;
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int align, size = type_size(&sv->type, &align);
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assert(!is_float(bt) || is_freg(r));
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if (bt == VT_STRUCT)
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tcc_error("unimp: store(struct)");
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if (size > 8)
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tcc_error("unimp: large sized store");
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assert(sv->r & VT_LVAL);
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if (fr == VT_LOCAL) {
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if (((unsigned)fc + (1 << 11)) >> 12)
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tcc_error("unimp: store(large local off) (0x%x)", fc);
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if (is_float(bt))
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tcc_error("unimp: store(float)");
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if (bt == VT_STRUCT)
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tcc_error("unimp: store(struct)");
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if (size > 8)
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tcc_error("unimp: large sized store");
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ES(0x23, size == 1 ? 0 : size == 2 ? 1 : size == 4 ? 2 : 3,
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8, rr, fc); // s[bhwd] RR, fc(s0)
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if (is_freg(r))
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ES(0x27, size == 4 ? 2 : 3, 8, rr, fc); // fs[wd] RR, fc(s0)
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else
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ES(0x23, size == 1 ? 0 : size == 2 ? 1 : size == 4 ? 2 : 3,
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8, rr, fc); // s[bhwd] RR, fc(s0)
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} else if (fr < VT_CONST) {
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int ptrreg = ireg(fr);
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ES(0x23, size == 1 ? 0 : size == 2 ? 1 : size == 4 ? 2 : 3,
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ptrreg, rr, 0); // s[bhwd] RR, 0(PTRREG)
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/*if (((unsigned)fc + (1 << 11)) >> 12)
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tcc_error("unimp: store(large addend) (0x%x)", fc);*/
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fc = 0; // XXX support offsets regs
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if (is_freg(r))
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ES(0x27, size == 4 ? 2 : 3, ptrreg, rr, fc); // fs[wd] RR, fc(PTRREG)
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else
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ES(0x23, size == 1 ? 0 : size == 2 ? 1 : size == 4 ? 2 : 3,
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ptrreg, rr, fc); // s[bhwd] RR, fc(PTRREG)
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} else if (sv->r == (VT_CONST | VT_SYM | VT_LVAL)) {
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static Sym label;
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int tempr, addend = 0;
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if (1 || ((unsigned)fc + (1 << 11)) >> 12)
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addend = fc, fc = 0;
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tempr = ireg(get_reg(RC_INT));
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greloca(cur_text_section, sv->sym, ind,
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R_RISCV_PCREL_HI20, addend);
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if (!label.v) {
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label.v = tok_alloc(".L0 ", 4)->tok;
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label.type.t = VT_VOID | VT_STATIC;
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}
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label.c = 0; /* force new local ELF symbol */
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put_extern_sym(&label, cur_text_section, ind, 0);
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o(0x17 | (tempr << 7)); // auipc TEMPR, 0 %pcrel_hi(sym)+addend
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greloca(cur_text_section, &label, ind,
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R_RISCV_PCREL_LO12_S, 0);
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if (is_freg(r))
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ES(0x27, size == 4 ? 2 : 3, tempr, rr, fc); // fs[wd] RR, fc(TEMPR)
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else
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ES(0x23, size == 1 ? 0 : size == 2 ? 1 : size == 4 ? 2 : 3,
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tempr, rr, fc); // s[bhwd] RR, fc(TEMPR)
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} else
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tcc_error("implement me: %s(!local)", __FUNCTION__);
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}
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@ -235,23 +328,68 @@ static void gcall(void)
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ST_FUNC void gfunc_call(int nb_args)
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{
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int i, align, size, aireg;
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aireg = 0;
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int i, align, size, aireg, afreg;
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int info[nb_args ? nb_args : 1];
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int stack_adj = 0, ofs;
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SValue *sv;
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Sym *sa;
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aireg = afreg = 0;
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sa = vtop[-nb_args].type.ref->next;
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for (i = 0; i < nb_args; i++) {
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size = type_size(&vtop[-i].type, &align);
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if (size > 8 || ((vtop[-i].type.t & VT_BTYPE) == VT_STRUCT)
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|| is_float(vtop[-i].type.t))
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int *pareg;
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sv = &vtop[1 + i - nb_args];
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sv->type.t &= ~VT_ARRAY; // XXX this should be done in tccgen.c
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size = type_size(&sv->type, &align);
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if (size > 8 || ((sv->type.t & VT_BTYPE) == VT_STRUCT))
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tcc_error("unimp: call arg %d wrong type", nb_args - i);
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if (aireg >= 8)
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tcc_error("unimp: too many register args");
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vrotb(i+1);
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gv(RC_R(nb_args - 1 - aireg));
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vrott(i+1);
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aireg++;
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pareg = sa && is_float(sv->type.t) ? &afreg : &aireg;
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if (*pareg < 8) {
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info[i] = *pareg + (sa && is_float(sv->type.t) ? 8 : 0);
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(*pareg)++;
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} else {
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info[i] = 16;
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stack_adj += (size + align - 1) & -align;
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}
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if (sa)
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sa = sa->next;
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}
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stack_adj = (stack_adj + 15) & -16;
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if (stack_adj) {
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EI(0x13, 0, 2, 2, -stack_adj); // addi sp, sp, -adj
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for (i = ofs = 0; i < nb_args; i++) {
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if (1 && info[i] >= 16) {
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vrotb(nb_args - i);
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size = type_size(&vtop->type, &align);
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/* Once we support offseted regs we can do this:
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vset(&vtop->type, TREG_SP | VT_LVAL, ofs);
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to construct the lvalue for the outgoing stack slot,
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until then we have to jump through hoops. */
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vset(&char_pointer_type, TREG_SP, 0);
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vpushi(ofs);
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gen_op('+');
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indir();
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vtop->type = vtop[-1].type;
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vswap();
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vstore();
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vrott(nb_args - i);
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ofs += (size + align - 1) & -align;
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ofs = (ofs + 7) & -8;
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}
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}
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}
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for (i = 0; i < nb_args; i++) {
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int r = info[nb_args - 1 - i];
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if (r < 16) {
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vrotb(i+1);
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gv(r < 8 ? RC_R(r) : RC_F(r - 8));
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vrott(i+1);
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}
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}
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vrotb(nb_args + 1);
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gcall();
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vtop -= nb_args + 1;
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if (stack_adj)
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EI(0x13, 0, 2, 2, stack_adj); // addi sp, sp, adj
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}
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static int func_sub_sp_offset;
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@ -433,10 +571,6 @@ static void gen_opil(int op, int ll)
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d = ireg(d);
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switch (op) {
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case '%':
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case '&':
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case '/':
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case '^':
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case '|':
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case TOK_SAR:
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case TOK_SHR:
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case TOK_UDIV:
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@ -457,6 +591,18 @@ static void gen_opil(int op, int ll)
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case '*':
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o(0x33 | (d << 7) | (a << 15) | (b << 20) | (0x01 << 25)); //mul d, a, b
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break;
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case '/':
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o(0x33 | (d << 7) | (a << 15) | (b << 20) | (0x01 << 25) | (4 << 12)); //div d, a, b
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break;
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case '&':
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o(0x33 | (d << 7) | (a << 15) | (b << 20) | (7 << 12)); // and d, a, b
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break;
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case '^':
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o(0x33 | (d << 7) | (a << 15) | (b << 20) | (4 << 12)); // xor d, a, b
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break;
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case '|':
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o(0x33 | (d << 7) | (a << 15) | (b << 20) | (6 << 12)); // or d, a, b
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break;
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case TOK_ULT:
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case TOK_UGE:
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